(1) Field of the Invention
The present invention relates to a solid-state imaging device including pixels which perform photoelectric-conversion on incident light and are arranged two-dimensionally on a semiconductor substrate.
(2) Description of the Related Art
A MOS image sensor has excellent characteristics, such as operating at a high-speed and providing a high-sensitivity, and the market for digital single lens reflex cameras (DSLR) equipped with the MOS image sensor is rapidly expanding recently. The MOS image sensor is utilized only for capturing a still picture in a conventional DSLR. For a finder of the DSLR, a conventional optical finder is employed. Meanwhile, becoming mainstream today is a camera featuring a live preview capability which displays, in real time, a monitor image on a small liquid crystal display installed of on the camera body, the monitor image which is detected by an image sensor. Thus, on most of image sensors, both of the progressive-scanning mode for capturing a still picture, and the pixel mixture mode for a live view are available.
FIG. 19 shows an overall structure of a conventional solid-state imaging device disclosed in Patent Reference 1.
An object of the solid-state imaging device is to improve a signal-to-noise (S/N) ratio in both of the pixel mixture mode in which pixel signals are mixed and a mode with no pixels mixed. The solid-state imaging device includes a signal processing unit 100, an image area (imaging area) 510 on which plural unit cells (pixels) 500 are two dimensionally arranged, a column signal line 520, a row selecting circuit 530, a load transistor group 540 connected to the column signal line 520, a column selecting circuit 560, a row common signal line 570, and an output amplifier 580 connected to the row signal common line 570.
Each pixel 500 includes a photodiode 501, a reading transistor 502, an amplifying transistor 503, a reset transistor 504, a column selection transistor 505, and a floating diffusion (FD) 506. In the pixels 500 on the n-th row, READ (n) is supplied to a gate of the reading transistor 502, RESET (n) to a gate of the reset transistor 504, and LSET (n) to a gate of the column selection transistor 505.
Citation List
Patent Literature
Patent Literature 1: Japanese Unexamined Patent Application Publication No. 2004-304771